Explain Cache Conflicts and Related Memory-Access Problems

Describe a cache-line conflict with a concrete address example, and then contrast it with false sharing and GPU shared-memory bank conflicts.

Constraints & Assumptions

The term "cache-line conflict" appears without a specific hardware context. Start by clarifying which mechanism is meant. For a concrete cache-set illustration, suppose a set-associative cache with line size L bytes, S sets, and A ways, using the set index floor(address/L) mod S.

Clarifying Questions

Is the issue cache-set eviction, coherence traffic between CPU cores, or serialization of scratchpad banks on a GPU? What is the access pattern, alignment, and hardware mapping?

What a Strong Answer Covers

A specific mapping from addresses to lines or sets, the resulting contention, and fixes suited to the actual mechanism.

Follow-up Questions

How can a working set that fits in total cache capacity still thrash? Why does padding help? When would padding only increase memory usage without resolving the bottleneck?

Overview: Describe cache-set conflicts via address mapping, then separate eviction from false sharing and GPU bank conflicts so that padding and layout changes address the correct cause.