Describe common RTL lint warnings and errors

You are writing RTL (for example, Verilog or SystemVerilog) and you run a lint tool on the code. The tool flags issues like:

• "Treat as black box"
• Combinational loop
• Left-hand side (LHS) / right-hand side (RHS) length mismatch (width mismatch) For each one, explain:

1. What condition typically triggers the warning or error.
2. Why leaving it unresolved can be risky.
3. How you would normally investigate and correct the problem in your RTL. Also briefly explain why linting matters in a digital design flow.

Overview: This question tests your grasp of RTL static analysis and frequent Verilog/SystemVerilog lint warnings and errors, including your ability to diagnose black-box modules, combinational loops, and width mismatches.