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Write a One-Hot SystemVerilog Constraint Without $onehot

Algorithm · Apple · Medium

The expression a & (a - 1) clears the least significant 1 bit in a. It equals zero only when a has zero or one set bit. The additional guard a != '0 removes the all-zero case, leaving exactly one-hot values. For N = 4, the allowed values are: For N = 1, the only legal randomized result is:

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